Server-Based Data Push Architecture for Multi-Processor Environments  

作　　者：孙贤和 Surendra Byna 陈勇 

机构地区：[1]Department of Computer Science Illinois Institute of Technology,Chicago,Illinois 60616,U.S.A.Computing Division,Fermi National Accelerator Laboratory.Batavia,IL 60510-0500,U.S.A. [2]Department of Computer Science Illinois Institute of Technology,Chicago,Illinois 60616,U.S.A.

出　　处：《Journal of Computer Science & Technology》2007年第5期641-652,共12页计算机科学技术学报（英文版）

基　　金：This research was supported in part by the National Science Foundation of U.S.A.under NSF Grant Nos. EIA-0224377,CNS-0406328,CNS-0509118,and CCF-0621435.

摘　　要：Data access delay is a major bottleneck in utilizing current high-end computing （HEC） machines. Prefetching, where data is fetched before CPU demands for it, has been considered as an effective solution to masking data access delay. However, current client-initiated prefetching strategies, where a computing processor initiates prefetching instructions, have many limitations. They do not work well for applications with complex, non-contiguous data access patterns. While technology advances continue to increase the gap between computing and data access performance, trading computing power for reducing data access delay has become a natural choice. In this paper, we present a serverbased data-push approach and discuss its associated implementation mechanisms. In the server-push architecture, a dedicated server called Data Push Server （DPS） initiates and proactively pushes data closer to the client in time. Issues, such as what data to fetch, when to fetch, and how to push are studied. The SimpleScalar simulator is modified with a dedicated prefetching engine that pushes data for another processor to test DPS based prefetching. Simulation results show that L1 Cache miss rate can be reduced by up to 97% （71% on average） over a superscalar processor for SPEC CPU2000 benchmarks that have high cache miss rates.Data access delay is a major bottleneck in utilizing current high-end computing （HEC） machines. Prefetching, where data is fetched before CPU demands for it, has been considered as an effective solution to masking data access delay. However, current client-initiated prefetching strategies, where a computing processor initiates prefetching instructions, have many limitations. They do not work well for applications with complex, non-contiguous data access patterns. While technology advances continue to increase the gap between computing and data access performance, trading computing power for reducing data access delay has become a natural choice. In this paper, we present a serverbased data-push approach and discuss its associated implementation mechanisms. In the server-push architecture, a dedicated server called Data Push Server （DPS） initiates and proactively pushes data closer to the client in time. Issues, such as what data to fetch, when to fetch, and how to push are studied. The SimpleScalar simulator is modified with a dedicated prefetching engine that pushes data for another processor to test DPS based prefetching. Simulation results show that L1 Cache miss rate can be reduced by up to 97% （71% on average） over a superscalar processor for SPEC CPU2000 benchmarks that have high cache miss rates.

关 键 词：performance measurement evaluation MODELING simulation of multiple-processor system cache memory 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]