基于Verilog HDL的有限状态机设计  

Design FSM by Verilog HDL

作　　者：方洪浩[1] 雷蕾[1] 常何民[1] 

机构地区：[1]中国科学院西安光学精密机械研究所

出　　处：《科学技术与工程》2007年第20期5278-5281,共4页Science Technology and Engineering

摘　　要：介绍Verilog硬件描述语言(HDL)历史及其特点,有限状态机(FSM)广泛适用于设计数字系统的控制模块,包括组合逻辑和寄存器逻辑,设计的可综合状态机有多种编码风格,语言描述较为抽象,通过研究总结一般编写状态机的方法、步骤和设计要点来设计一个自动转换量程的频率计控制器并对之进行仿真。The history and the characteristic of the Verilog Hardware Description Language are introduced. Finite state machine is extensively used in designing the control module of the digital system, including combinational logic and register logic. The designed synthesis state machine has lots of coding styles. The language description is relatively abstract. A cymometer controller which owns the auto switchover measurement function is designed and simulated through investigating and summarizing the methods, processes and design main of compiling the common state machine.

关 键 词：VERILOG HDL FSM 频率计控制器 同步时序方式 编码风格 

分 类 号：TP332.11[自动化与计算机技术—计算机系统结构]