基于DSP和CPLD的数字锁相技术研究  

Research on phase locked loop based on DSP and CPLD

作　　者：王青松[1] 李迪安[1] 张仲超[1] 

机构地区：[1]浙江大学电气工程学院,浙江杭州310027

出　　处：《机电工程》2007年第10期58-60,共3页Journal of Mechanical & Electrical Engineering

摘　　要：提出了一种基于数字信号处理技术(DSP)和可编程逻辑控制器件(CPLD)的全数字锁相方法。首先实现了DSP与CPLD的相互通信,在此基础上详细阐述了锁相的基本原理,并分别给出了DSP和CPLD的程序算法和设计流程,最后通过实验验证了该方法的正确性和可行性。实践证明,该技术具有广泛的推广应用前景。A new method of digital phase locked loop based on digital signal processing （DSP） and complex programmble logic device （CPLD） was proposed. Firstly, the communication between DSP and CPLD was realized, and the basis of communication, the principle of digital phase locked loop was illustrated. Finally, the program algorithm and its process were given. The experimental results prove that the method has validity and feasibility, it illustrates a good prospect of application and extension.

关 键 词：数字信号处理技术 可编程逻辑器件 数字锁相 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]