一种乘积码译码器设计方案的研究  

Research into Iterative Decoder Design for Product Code

作　　者：郭丽[1] 蒋卓勤[1] 

机构地区：[1]西安通信学院基础部,陕西西安710106

出　　处：《电子科技》2007年第10期61-63,共3页Electronic Science and Technology

摘　　要：介绍了一种乘积码迭代译码器的硬件设计方案。基于软判决译码规则,使用VHDL硬件描述语言,提出了基于Modelsim6.Oa仿真平台的两维乘积码的EDA实现方法,给出了仿真波形,迭代次数为四次时最大译码速率可达到50Mbit/s,并通过了在Xilinx公司的FPGA芯片XC2S200上的综合验证实验。该译码器的功能仿真和硬件实现都证明了这种方案的可行性和正确性。This paper introduces a hardware design of two dimensional product code iterative decoder. Based on soft - decision decoding principles, this paper proposes an EDA realization of 2 - D product code iterative decoder based on MODELSIM 6. 0a, which is described in VHDL language. The simulated waveform is also given. This decoder is implemented on a FPGA circuit（Xilinx- xc2s300）, which is capable of achieving a data rate of 50Mbps with four iterations. Both the simulation results andthe implementation prove the validity and feasibility of the design.

关 键 词：乘积码 软判决译码 外信息 迭代译码 VHDL FPGA EDA 

分 类 号：TN919.32[电子电信—通信与信息系统]