SiGe SOI CMOS特性分析与优化设计  

Characteristics Analysis and Optimal Design of SiGe SOI CMOS

作　　者：高勇[1] 黄媛媛[1] 刘静[1] 

机构地区：[1]西安理工大学自动化学院电子工程系,西安710048

出　　处：《微电子学》2007年第5期619-623,共5页Microelectronics

基　　金：西安-应用材料创新基金资助项目(XA-AM-200514)

摘　　要：基于全耗尽SOI CMOS工艺,建立了具有Si Ge沟道的SOI MOS器件结构模型,并利用ISE TCAD器件模拟软件,对Si Ge SOI CMOS的电学特性进行模拟分析。结果表明,引入Si Ge沟道可极大地提高PMOS的驱动电流和跨导(当Ge组分为0.3时,驱动电流提高39.3%,跨导提高38.4%),CMOS电路的速度显著提高;在一定的Ge总量下,改变Ge的分布,当沟道区呈正向递减式分布时,电路速度最快。Based on fully-depleted SOI technology, a two-dimensional MOS structure model comprising SiGe channel was established. By employing ISE TCAD, simulations were made on electrical characteristics to predict and investigate driving ability and speed performance. Result showed that the drive current and circuit speed could be improved significantly by using SiGe channel. The drive current and transconductance increased by 39. 3%and 38. 4 %, respectively, for 30 % Ge composition. Furthermore, optimal performance could be achieved by modulating Ge distribution to a positive degressive trend for a fixed Ge content.

关 键 词：全耗尽SOI SIGE CMOS 迁移率 驱动电流 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN304.24