板级电子封装跌落／冲击中焊点应力分析  

Drop/Impact Stress Analysis of Solder Joints in Board Level Electronics Package

作　　者：秦飞[1] 白洁[1] 安彤[1] 

机构地区：[1]北京工业大学机械工程与应用电子技术学院,北京100022

出　　处：《北京工业大学学报》2007年第10期1038-1043,共6页Journal of Beijing University of Technology

基　　金：国家自然科学基金(10572010);北京市教委科技发展计划项目(KM200610005013);北京市先进制造技术重点实验室开放课题资助项目(102KB00732).

摘　　要：建立了板级BGA封装跌落/冲击问题的三维有限元模型,采用Input-G方法对PCB板的变形及焊锡接点应力等动力学响应进行了分析,探讨了约束条件对计算结果的影响,对焊点剥离应力产生的机理进行了讨论,提出了快速估算焊点应力的等效静力学模型并分析了误差.结果表明,模型中PCB板固定螺栓处的约束条件处理对结果有较大影响,合理的处理方法是在PCB板4个螺栓作用区的上下表面均施加水平方向位移约束.焊点应力最大值出现在冲击后0.4 ms,最大剥离应力发生在角部焊点与PCB板一侧的铜垫交界处.焊点应力与PCB板的弯曲变形密切相关,应力峰值和PCB板的变形峰值在时间上具有同步性.挠度等效静力学模型得到的焊点应力比动力学模型高23%左右.A 3-D finite element model of board level BGA package was built and the Input-G method was used to analyze dynamic solder joint stress in the package during drop/impact. Boundary condition, bolt effects of the test board and peeling stress mechanism were emphasized in current investigation. An equivalent static model that can evaluate stress quickly was proposed. The results show that bolt constraints have a significant influence on the dynamic stress in solder joints. The bolt constraints must be treated as zero horizontal dis- placement in the area the bolt acted in the numerical model. The stress in the solder joint reaches its peak at 0.4ms and the maximum peeling stress is located at the most outer corner of the package. The peeling stress is dominated by the deflection of the PCB board. The equivalent static model predicts the same stress distribution in the package but overestimates the stress about 23 %.

关 键 词：电子封装 跌落/冲击 焊锡接点 可靠性 有限元 

分 类 号：TB12[理学—工程力学] TN47[理学—力学]