基于Verilog HDL的流水线模型机的设计与实现  

Design and Implementation of a Pipeline Model Machine Based on Verilog HDL

作　　者：易小琳[1] 彭一凡[1] 

机构地区：[1]北京工业大学计算机学院,北京100022

出　　处：《北京工业大学学报》2007年第10期1096-1101,共6页Journal of Beijing University of Technology

摘　　要：为了提高模型机指令执行的并行性,使用Verilog HDL并采取top-down设计方法,利用确定的有限状态自动机(DFA)理论,设计并实现了一台具有指令级并行性的流水线模型机的方案.阐述了该流水线模型机的DFA设计算法与Verilog HDL的实现方法,并给出了相应的仿真测试.测试结果证明,该模型机能并行处理4条指令,并具有预取指令和旁路功能.In order to raise parallelism of executing instructions by model machine, this paper introduces the schema of designing a pipeline model machine. Using Verilog HDL, a pipeline model machine with parallelism of instructions which is combined with top-down method and DFA is implemented. This paper describes the schema and some algorithms of the pipeline model machine and simulates this machine in the end. The simula- tion results show that the model machine can process 4 instructions at the same time, and has the per-for- mances of pre-fetching instructions and bypassing.

关 键 词：流水线 VERILOG HDL描述 微处理器 确定的有限状态自动机 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]