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机构地区:[1]大连理工大学电子与信息工程学院,辽宁大连116024
出 处:《中国电子商情(通信市场)》2007年第10期32-36,共5页
摘 要:通信系统中往往采用数字复接技术来扩大信息的传输容量并提高信道利用率。本文利用CPLD器件完成了8路视频数字信号的复接过程。同时,控制时钟信号也由同一个CPLD器件来产生,更好的解决了复接与分接中的同步问题。该设计的控制模块由VHDL语言完成,最后利用Altera公司的Quartus II6.0工具完成了该设计的行为仿真及时序仿真。仿真结果验证了输入输出的逻辑关系。The digital multiple connection technique is usually applied to expand the capacity of the information transmission and raise the efficiency of the channel in communication system. In this paper, 8 channels video digital multiple connections were accomplished by CPLD device. At the same time, the control timing signals were produced in the same chip in order to solve problem of synchronization suitably. The design's module of control was compiled by VHDL language; at last, its behaves and timing simulation were accomplished by Quartus II 6.0 launched by Altera. The logic relationship of input and output was validated by simulation result.
分 类 号:TN913.7[电子电信—通信与信息系统]
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