VelociTI结构浮点DSPs寄存器堆读写的流水线设计  

Pipeline Design for Reading and Writing of Register File of DSPs Based on VelociTI Architecture

作　　者：胡正伟[1] 仲顺安[1] 陈禾[1] 

机构地区：[1]北京理工大学电子工程系

出　　处：《计算机工程》2007年第21期237-239,共3页Computer Engineering

基　　金：国家部委预研基金资助项目(200205)

摘　　要：研究了VelociTI结构浮点数字信号处理器寄存器堆的流水线读写原理并提出了一种设计方法。该方法对单操作数双精度浮点指令采用2个32位数据通路用1个流水线周期读取源操作数,双操作数双精度浮点指令采用锁定译码单元,利用若干流水线周期读取源操作数。采用写控制向量的方法实现了流水线多个周期执行写操作。该方法正确实现了基于IEEE754标准的双精度浮点数据在寄存器堆与功能单元之间的32位数据通路上的传输,仿真结果验证了其正确性。Principle of reading and writing of register file of digital signal processor based on VelociTI architecture is studied and one design method is proposed. Reading of single operand double precision floating point instructions is accomplished by using two 32 bits data path in one pipeline cycle. For two-operand double precision floating point instructions, decode unit is locked until all operands are accessed. Writing control signal vector is adopted for writing. Double precision floating point data based on IEEE754 standard can be accessed with 32 bits data path by using this method. The correctness is conformed by simulation results.

关 键 词：VelociTI结构 流水线 寄存器堆 浮点数据 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]