性能改进的16位超前进位加法器  

A 16-bit CLA with Improved Performance

作　　者：李嘉[1] 蒋林[1] 

机构地区：[1]西安邮电学院,陕西西安710061

出　　处：《现代电子技术》2007年第22期172-174,共3页Modern Electronics Technique

摘　　要：加法运算是最重要最基本的运算,所有的其他基本算术运算,减、乘、除、模乘运算最终都能归结为加法运算。在不同的场合使用的加法器对其要求也不同,有的要求速度更快,有的要求面积更小。基于速度更快的要求,对3种常用加法器从结构与性能上进行比较,给出了综合面积与速度的比较。进而对超前进位加法器进行了进一步改进,加入了流水线结构设计,大大提高了其速度性能。The addition operation is the most important fundamental operation,all other operations including subtraction multiplication division and modular multiplication can be implemented by addition operation. Adders using at various cases are different since the requirement are different. Some ask for faster,others ask for smaller. Three common used adders are compared in the structural and performance, based on the requirement of faster. Then some ameliorations on the CI.A are made by adding pipline structure to improve its performance for working faster.

关 键 词：串行进位加法器 超前进位加法器 流水线 逻辑综合 

分 类 号：TP342.21[自动化与计算机技术—计算机系统结构]