Low Jitter,Dual-Modulus Prescalers for RF Receivers  

射频接收机中低抖动双模分频器(英文)

作　　者：唐路[1] 王志功[1] 何小虎[1] 李智群[1] 徐勇[1] 李伟[1] 郭峰[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《Journal of Semiconductors》2007年第12期1930-1936,共7页半导体学报（英文版）

摘　　要：Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.对射频接收机中双模分频器的设计和应用进行了研究.提出了一种改进型D-latch以提高双模分频器速度与驱动能力,一种将D-latch与"或"逻辑门集成的结构以降低电路的复杂度.采用TSMC0.18μm CMOS混合信号工艺实现了用于地面数字电视接收机的除16/17双模分频器.采用0.18μmCMOS标准单元库设计并以与双模分频器同样的工艺实现了可编程吞吐式脉冲分频器.测试结果显示双模分频器的输出抖动小于0.03%,而且能够与可编程吞吐式脉冲分频器良好地配合工作.

关 键 词：PLL frequency synthesizer DMP programmable ＆ pulse swallow divider 

分 类 号：TN772[电子电信—电路与系统]