基于门控时钟的低功耗CAVLC解码器设计  

Design of Low Power CAVLC Decoder Based on Clock-gating

作　　者：陈光化[1] 万芬芳[1] 翟海华[1] 

机构地区：[1]上海大学微电子研究与开发中心,上海200072

出　　处：《电视技术》2007年第12期23-25,共3页Video Engineering

基　　金：上海市重点学科建设项目(T0103);上海市教委项目(A10-0109-06-022)

摘　　要：提出了一种应用于H.264/AVC的低功耗上下文自适应变长编码(CAVLC)解码器的设计方案。对各解码块和内部寄存器分别采用模块级和寄存器级的时钟门控,关闭空闲的时钟,降低了解码器的动态功耗。该设计采用0.25μm工艺,在100MHz时钟约束下,对门控后的解码器进行功耗分析,结果证明CAVLC解码器的功耗降低了65%。On the premise of the same performance,according to the decoding flow of the decoder,clock gating is employed at module level and register level respectively. The clock of those idle modules and registers is shut off. This method saves the deoder＇s dynamic power. Under a 0.25 μm technology and at clock constraint of 100MHz,the power of gated CAVLC decoder is analyzed. The result shows that the power of CAVLC decoder is reduced as much as 65%.

关 键 词：H.264 AVC标准 上下文自适应变长编码 解码器 门控时钟 

分 类 号：TN919.81[电子电信—通信与信息系统]