Viterbi译码器路径度量模块的低功耗设计  

Low power design for path metrics unit of viterbi decoder

作　　者：姜淼[1] 陈亦灏[1] 徐俊[1] 陶佰睿[1] 李刚[1] 

机构地区：[1]华东师范大学,上海200062

出　　处：《齐齐哈尔大学学报（自然科学版）》2007年第6期41-44,共4页Journal of Qiqihar University(Natural Science Edition)

摘　　要：从功耗的角度,对符合DVB-T标准的维特比译码器的路径度量单元进行了优化设计。为了实现低功耗设计,加比选单元采用了改进的T算法来实现,同时路径度量值只需要5位表示;路径度量管理单元采用了串并结合的结构来实现,并采用了5级流水线的路径度量存储结构。This paper does a research on low power design for the path metrics unit of Viterbi decoder which is compatible with DVB-T standards. In order to reduce the power dissipation, the modified T-algorithm is used to implement the add-compare-select units so that the path metric can be represented in 5 bits; the area-efficient architecture is used in the path metric management unit; and a 5 step pipelining architecture is used in the path metric memory unit.

关 键 词：DVB-T 卷积码 维特比译码器 FPGA 

分 类 号：TN915.05[电子电信—通信与信息系统]