高速Viterbi译码器的VLSI设计与实现  

VLSI Design and Implementation of a High-Speed Viterbi Decoder

作　　者：李庆[1] 邓运松[1] 曾晓洋[1] 顾叶华[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《计算机研究与发展》2007年第12期2143-2148,共6页Journal of Computer Research and Development

基　　金：国家自然科学基金项目(90407002;60576024);上海市科委AM基金项目(0502)

摘　　要：在优化结构的基础上,实现了一种回溯长度为64的(2,1,7)高速Viterbi译码器.该译码器采用改进的加比选单元(ACS),降低了硬件复杂度,提高了时钟运行频率.改进的回溯单元采用了分块循环存储器,对数据读取结构进行改进,提高了译码器的数据吞吐率.基于SMIC0.18μmCMOS工艺,该译码器最高工作时钟频率可达180MHz,等效逻辑门约为28683门.经过验证比较,结果表明实现的高速Viterbi译码器在各个指标上如实现面积、回溯长度和约束长度比现有的各种方案有较大幅度的提高,因此该译码器在数字通信领域具有良好的应用前景如DTV和HDTV.Based on an optimized structure, a high-speed （2,1,7） Viterbi decoder with trace-back length of 64 is presented in this paper. Considering the punctured convolutional codes for Viterbi decoding and the hardware complexity of its implementation, a modified ACS （add-compare-select） unit is used to satisfy its decoding requirements and reduce its hardware complexity. Also, a parallel structure is adopted to meet the working speed requirements but does not increase its hardware complexity. In order to increase its decoding throughput rate, the decoder employs blocked cyclic memory, which is composed of register file that can help reduce the implementation size of the decoder. A new trace-back unit is introduced to improve the way of data reading and writing for trace-back. Implemented by SMIC 0.18μm standard CMOS technology, its hardware scale is about 28 683 gates （2 input NAND is counted as a gate）, and the highest speed is about 180MHz. Compared with other reported schemes, the performances of this proposed Viterbi decoder are better in terms of implementation size, throughput rate and constraint length. With the above excellent performances, the proposed Viterbi decoder is very suitable to be applied in the field of digital communication, which needs high throughput rate and small implementation size, such as DTV and HDTV.

关 键 词：维特比译码器 加比选 高速 回溯 HDTV 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]