基于DA算法的高速高阶FIR滤波器的FPGA实现  

Implementation of High-speed and High-tap FIR Filter Based on Distributed Arithmetic and FPGA

作　　者：孙建明[1] 赵刚[1] 张迎华[1] 

机构地区：[1]西南石油大学计算机科学学院,四川成都610050

出　　处：《信息与电子工程》2007年第6期432-436,共5页information and electronic engineering

摘　　要：针对在数字信号处理中,以专用DSP芯片设计高阶有限长单位冲激响应(FIR)滤波器速度较慢的情况,提出了一种基于分布式算法(DA)和现场可编程门阵列(FPGA)实现高速高阶滤波器的新方法,并以一个16阶FIR滤波器在Xilinx公司的xc2v500芯片上实现为例说明了设计过程,仿真结果表明:电路工作正确可靠,满足设计要求。In the digital signal processing, the high-tap FIR filter with special DSP chip works slowly. In order to solve the mentioned problem, this paper introduces a new method to implement high-speed and high-tap filter based on distributed arithmetic（DA） and field programmable gate array（FPGA）. As an illustrative instance, 16-tap finite impulse response （FIR） filter is designed with the Xilinx Corporation＇ s xc2v500 chip in detail. The experimental results suggest the system is reasonable and reliable and can satisfy the design requirements by simulation and synthesis.

关 键 词：DA算法 FIR滤波器 硬件描述语言 现场可编程门阵列 

分 类 号：TN713[电子电信—电路与系统]