槽栅型肖特基势垒静电感应晶体管  

V-Groove Recessed-Gate Schottky Barrier Static Induction Transistor

作　　者：杨涛[1] 刘肃[1] 李思渊[1] 王永顺[2] 李海蓉[1] 

机构地区：[1]兰州大学物理科学与技术学院微电子学研究所,兰州730000 [2]兰州交通大学电子与信息工程学院电子科学与技术系,兰州730070

出　　处：《半导体技术》2008年第1期65-67,共3页Semiconductor Technology

摘　　要：传统的静电感应晶体管多采用扩硼的方法制备栅极区,这种工艺热预算较高,使得工艺复杂程度和生产成本较高,基于此提出并设计了一种新型的槽栅型肖特基势垒静电感应晶体管。使用V形槽工艺,用溅射铝的方法代替扩硼工艺制备静电感应晶体管的栅极区,简化了工艺流程,使器件在调试过程中具有很大灵活性。使用PECVD(等离子体增强化学气相淀积)工艺,解决了槽栅结构静电感应晶体管的栅极区与源极区容易短路的问题。给出了详细的工艺流程。The gate region of conventional SIT （static induction transistor） is usually prepared by B diffusion in n-type Si, the preparation is complex and high in cost, so a new recessed-gate Schottky barrierSIT was proposed. The gate region was fabricated by V-groove and A1 sputtering, process, and make devices flexible in the adjustment process. By PECVD the short which can simplify the circuit problem between the source region and the gate region in recessed-gate SIT can be avoid. The main steps for process were given.

关 键 词：静电感应晶体管 V形槽 等离子体增强化学气相淀积 肖特基势垒 

分 类 号：TN386.3[电子电信—物理电子学]