LPCC浮点运算IP核的设计与实现  

Design and Implementation of LPCC Floating-Point Extraction IP Core

作　　者：李倩[1] 侯义斌[1] 黄樟钦[1] 何东之[1] 王晋嘉[1] 赵丽娜[1] 高曦[1] 

机构地区：[1]北京工业大学嵌入式软件与系统研究所,北京100022

出　　处：《微电子学与计算机》2008年第1期85-88,92,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(90407017);北京市教委基金项目(KP2701200201)

摘　　要：介绍了线性预测倒谱系数(Linear Prediction Cepstrum Coefficient,LPCC)提取算法,给出该算法的一种浮点IP核实现模型,并详细描述了各个子模块的设计方法。以VHDL作为设计语言,在ISE、ModelSim软件下完成综合和仿真,并在Xilinx Spartan-3 FPGA目标板上实现设计。采用关键路径流水线实现、资源共享等技术进行优化。该IP核计算结果精度高,运算时间短,已经成功应用在嵌入式语音识别系统中。This paper introduces （Linear Prediction Cepstrum Coefficient,LPCC）extraction algorithm, proposes a floating-point IP core implementation modal of this algorithm, and describes the design of each sub-module in detail. The design is described with VHDL; synthesis and simulation is completed by ISE and ModelSim development tools. Finally, it has been implemented in Xilinx Spartan-3 FPGA board. This IP core adopts some optimized methods, such as pipeline structure, resource-sharing structure. It has high precision and short process time. It has been used in embedded speech recognition system successfully.

关 键 词：IP核 线性预测倒谱系数 FPGA 语音识别 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]