12位100MS/s流水线A/D转换器的参考电压缓冲器  

A Voltage Reference Buffer for 12-Bit 100MHz Pipelined A/D Converter

作　　者：胡晓宇[1] 周玉梅[1] 王晗[1] 沈红伟[1] 戴澜[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学》2008年第1期133-136,144,共5页Microelectronics

摘　　要：分析了参考电压精度对流水线A/D转换器性能的影响,并通过Matlab建模仿真,得到了12位流水线A/D转换器对参考电压精度的要求,即参考电压精度要达到10位以上。提出了一种新型的参考电压缓冲器结构,通过增加两个静态比较器,有效地提高了缓冲器的精度。采用SMIC 0.35μm 3.3 V CMOS工艺,为一个12位100 MHz采样频率的流水线A/D转换器设计了电压值为1.65 V±0.5 V的参考电压输出缓冲器。Hspice后仿真结果显示,各个工艺角下,缓冲器可将干扰对1 V的差分输出的影响控制在0.35 mV以内。该缓冲器可以达到10位以上精度,能够满足12位100 MS/s流水线A/D转换器的设计要求。Influence of the variation of reference voltages on the performance of the pipelined A/D converter was analyzed. By simulating the model of the 12-bit pipelined A/D converter in Matlab, the requirement of reference voltages was obtained： the resolution of reference voltages in 12-bit pipelined A/D converter should be above 10-bit. Based on the analysis of different buffer architectures and with the full-scale of A/D converter taken into consideration, a novel buffer was proposed. Based on the proposed architecture, a voltage reference buffer of 1.65 V±0. 5 V was designed for a 12-bit 100 MS/s pipelined A/D converter. Hspice post-simulation in SMIC＇s 0. 35 μm 3.3 V CMOS process showed that the fluctuation of reference voltages was within 0. 3 mV, which meets the requirement of 12-bit 100 MS/s pipelined A/D converter.

关 键 词：流水线A/D转换器 参考电压 缓冲器 

分 类 号：TN792[电子电信—电路与系统]