45nmCMOS工艺下的低泄漏多米诺电路研究  

Low Leakage Domino Circuit Design for 45nm CMOS Technology

作　　者：杨松[1] 王宏[1] 杨志家[1] 

机构地区：[1]中国科学院沈阳自动化研究所

出　　处：《微电子学与计算机》2008年第2期89-92,共4页Microelectronics & Computer

摘　　要：在研究了45nm CMOS工艺下晶体管泄漏电流特性的基础上,提出了一种可以同时减小多米诺逻辑电路亚阈值和栅极氧化层泄漏功耗,带有NMOS睡眠开关并使用双阈值电压、双栅极氧化层厚度的电路技术。该电路技术与标准的双阈值电压多米诺逻辑电路相比,待机模式时消耗的总泄漏功耗在110℃时最高可以减小65.7%,在25℃时最高可以节省达94.1%。Based on the leakage current characteristics of transistors in 45nm CMOS technology, A low leakage circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate-oxide leakage power in domino logic circuits with NMOS sleep transistors. Dual threshold voltage and dual gate insulator thickness CMOS technologies are utilized to place an idle domino logic circuit into a low leakage state. The proposed circuit technique reduces the total leakage power by up to 65.7% at a temperature of 110℃ and 94.1% at the room temperature as compared to the standard dual threshold voltage domino logic circuits.

关 键 词：多米诺逻辑 阈值电压 亚阈值泄漏 栅极氧化层 

分 类 号：TN402[电子电信—微电子学与固体电子学]