基于并行预测的前导零预测电路设计  

Design of leading zero anticipation circuit based on parallel anticipation

作　　者：孙岩[1] 张鑫[1] 金西[1] 

机构地区：[1]中国科学技术大学物理系微电子学教研室,合肥230026

出　　处：《电子测量技术》2008年第1期84-87,共4页Electronic Measurement Technology

摘　　要：前导零预测电路是提高浮点加法器运算速度的一个重要手段,本文提出了一种适用于高速浮点加法器的前导零预测电路。它采用了独特的并行预测算法来分别预测做浮点减法运算时结果为正和为负的两种情况下的前导零数,再通过尾数运算结果的进位来判断运算结果的正负并对前导零预测的结果进行选择。该方法使得浮点减法运算前无需比较尾数的大小,且并行的预测算法共用部分逻辑电路,从而使加法器在运算速度提高的基础上降低了加法器的面积。最终的验证结果表明该方法正确有效。The algorithm and its implementation of the leading-zero anticipation（LZA） is very vital for the performance of a high-speed floating-point adder in today＇s microprocessor design. Unfortunately, most LZA based on the assumption that the output of the adder is always positive, which means the two operators have to be compared before the addition. This paper presents a new LZA logic for high-speed floating-point addition. It introduces a pair of fast parallel anticipatory arithmetic to anticipate leading-zero bits of the result of subtraction without knowing whether the result is positive or negative, thus it doesn＇t need to compare the fractions of the two operators before the addition. At the same time the proposed parallel logics share part of the circuit. Therefore, not only the speed of the adder rises but also the area declines. The evaluation of this algorithm is also presented in this paper and the results of the simulation demonstrate that this method is valid.

关 键 词：前导零预测电路 浮点加法器 IEEE754 并行预测 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]