用Verilog HDL进行FPGA设计的原则与方法  

Methods and principia of FPGA design using Veriog HDL

作　　者：祁晓磊[1] 蔡学良[1] 孙德玮[1] 

机构地区：[1]合肥电子工程学院,合肥230037

出　　处：《电子测试》2008年第3期67-71,共5页Electronic Test

摘　　要：Verilog HDL是目前较流行的一种硬件描述语言,在FPGA设计中有着广泛的应用。本文首先介绍了Verilog HDL语言的特点以及用其进行FPGA硬件开发的原则,然后在熟悉FPGA的硬件结构原理的基础上,遵循FPGA设计流程,以分频器和状态机为例,分别讨论了组合逻辑电路和时序逻辑电路各自的特点及其设计输入方法;最后结合FPGA的硬件特点,分析了将用Verilog HDL语言设计的电路的进行综合与设计优化并最终实现为硬件电路的方法。As a popular hardware description language, Verilog HDL has widely used in FPGA design. Firstly, the characteristic of Verilog HDL and the method of FPGA design using Verilog HDL is introduced; then keeping to the designing flow and taking frequency separation and state machine as exampies, the paper discusses the characteristic and the methods to design Combination Logic circuit and Sequential Logic circuit which based on the acquaintance with the configuration of FPGA ; lastly, combined the characteristic of FPGA, this paper discusses the methods to synthesize and optimize the circuit designed by Verilog HDL witch is lastly implemented into hardware circuit.

关 键 词：FPGA Vefilog HDL EDA 硬件描述语言 

分 类 号：TN791[电子电信—电路与系统]