高阶∑△ADC中积分器的设计  

Design of an integrator used in high order ∑△ADC

作　　者：朱军[1] 龚敏[1] 周长胜[2] 叶英[3] 

机构地区：[1]四川大学微电子技术四川省重点实验室,四川成都610065 [2]中科院嘉兴中心电子设计与应用分中心,浙江嘉兴314000 [3]湖南大学微电子学院,湖南长沙410082

出　　处：《电子技术应用》2008年第3期41-44,共4页Application of Electronic Technique

摘　　要：基于N阱0.6μm DPDM CMOS工艺,完成了高阶∑△ADC中第一级积分器的设计。分析了开关电容积分器的非理想特性,同时设计了一个对寄生电容不敏感的同相开关电容(SC)积分器,并特别采用旁路电容减小沟道电荷注入引起的谐波失真和噪声。在cadence下的电路仿真表明,积分器具有-104.9dB等效输入噪声;利用MATLAB进行系统仿真,∑△ADC的信号噪声畸变比(SNDR)达到100.5dB,满足系统16bit的要求。The first integrator of high order ∑Δ ADC is designed based on the N well 0.6μm DPDM CMOS technology. The nonideal characteristics of switched capacitor （SC） integrators is analysed in detail, and a noninverting SC integrator that is insensitive to parasitic capacitors is presented, with shunt capacitors especially to reduce the harmonic distortion and noise caused by channel charge injection. The circuit simulation in cadence shows that the integrator has input referred noise power of -104.9dB. Meanwhile, the system simulation in MATLAB indicates it meets the requirement of 16bit when SNDR reaches 100.5dB.

关 键 词：开关电容 积分器 电荷注入 共模反馈 

分 类 号：TN792[电子电信—电路与系统] TN432