基于Verilog的RISC MCU中断系统的设计与验证  

The design and verification of RISC MCU′s interrupt system based on Verilog

作　　者：凌朝东[1] 柯志斌[1] 王加贤[1] 

机构地区：[1]元顺集成电路设计中心华侨大学信息学院,福建泉州362021

出　　处：《电子技术应用》2008年第3期48-51,共4页Application of Electronic Technique

基　　金：福建省自然科学基金(A0640005);厦门市科技计划项目(3502Z20073037)

摘　　要：详细论述了4位RISC MCU中断系统的Verilog设计实现过程。该MCU采用PIC两级流水线结构,含4个中断源,2级优先级。最后通过整体的RISC MCU IP核对其中断系统进行完整的程序测试,完成功能与时序的仿真与验证。The process of design and realization of 4-bit RISC MCU＇s interrupt system based on Verilog is illustrated in detail. The MCU adopts two-stage pipeline architecture of PIC, includes four interrupt sources and two priority ranks. Finally, program tests using instructions are carried out through the whole RISC MCU IP core, simulation and verification in function and timing are presened.

关 键 词：VERILOG PIC RISC MCU 仿真 中断 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论] TP332[自动化与计算机技术—计算机科学与技术]