CMOS运放电路拓扑结构自动综合  

Automatic synthesis of CMOS Op-amp circuit

作　　者：高雪莲[1] 高鹏[1] 刘煜峰[1] 

机构地区：[1]华北电力大学电气与电子工程学院,北京102206

出　　处：《电路与系统学报》2008年第1期35-39,共5页Journal of Circuits and Systems

摘　　要：本文提出一种新的基于生成的CMOS运放电路拓扑结构自动综合方法和模拟电路的数据阵列描述方法。CMOS运放电路拓扑结构自动综合方法克服了基于选择的拓扑设计方法依赖设计者经验和基于生成的拓扑设计方法难以利用电路设计成功经验的局限,从若干经验子电路结构开始运放电路自动生成,在不出现无效电路结构的前提下,保证生成出电路拓扑结构的质量。模拟电路的数据阵列描述方法在数据阵列表述中融入成功的设计经验,能有效地解决多端器件的电路连接问题。最后论文利用该CMOS运放电路拓扑结构自动综合方法生成两个性能特点不同的运放电路,并对电路参数进行合理确定和spice电路仿真。We present a method for automatic synthesis of CMOS op-amp circuit and a data array description method of analog circuit. This new technique of circuit synthesis overcomes the limits of selection-based circuit design technique which relies on the designer＇s experience and the limits of construction-based circuit design technique which is difficult to take advantage of the successful experience of circuit design. With the prerequisite of no invalid circuit structure, this new technique, starting from classic sub-circuit model, automatically creating op-amp circuit, guarantees the quality of circuit construction. The data array description method of analog circuit, based on successful design experience, is able to solve the circuit connection problem of multiple terminal devices effectively. Results are reported to validate the effectiveness of this approach for topology-design automation of CMOS op-amp circuit.

关 键 词：CMOS运放电路 拓扑设计 自动综合 数据阵列描述方法 

分 类 号：TN43[电子电信—微电子学与固体电子学]