功耗限制下的NoC测试端口的优化选择方法  

An optimized test ports selecting method under power constraint in NoC

作　　者：欧阳一鸣[1] 冯伟[1] 梁华国[1] 

机构地区：[1]合肥工业大学计算机与信息学院,合肥230009

出　　处：《计算机应用》2008年第4期1026-1028,1031,共4页journal of Computer Applications

基　　金：国家自然科学基金资助项目(90407008;60633060);安徽省自然科学基金资助项目(050420103)

摘　　要：提出了一种NoC测试端口位置和数量的优化选取的方法,它在系统功耗限制的条件下,确定input/output端口的对数,以所有核测试路径总和最短为目标,优化选取NoC测试端口的最佳位置。本方案在测试功耗不超过系统允许的最大功耗条件下,最大限度地选取测试端口的对数来进行并行测试,从而能高效地完成对核的测试,同时又能有效地避免因测试带来的器件损坏。实验结果表明这种方法提高了测试效率,降低了NoC的总体测试代价。An optimized test ports selecting method was proposed, in which the number and location of input/output pairs under power constraint could be determined. To make the length of all the core test paths shortest, the optimized location of the Network on Chip （NoC） test ports were selected. With the constraint of the max permitted power in the test, the number of the test ports pairs was chosen as large as possible. Thus the test of the cores could be accomplished with high performance, and the apparatus damage in the test could be avoided effectively. Experimental results show that the efficiency of the test is improved and the overall cost in the NoC test is decreased.

关 键 词：片上系统 片上网络 测试访问机制 

分 类 号：TP391.76[自动化与计算机技术—计算机应用技术]