JPEG2000中算术编码的VLSI结构设计  

VLSI Architecture of Arithmetic Coding in JPEG2000

作　　者：乔世杰[1] 樊炜[1] 高勇[1] 

机构地区：[1]西安理工大学电子工程系,西安710048

出　　处：《电子器件》2008年第2期492-495,共4页Chinese Journal of Electron Devices

摘　　要：算术编码算法对于无损数据压缩是一种非常有效的方法,它已经被JPEG2000标准所采用。通过研究JPEG2000标准中的算术编码算法,设计了一种算术编码器的VLSI结构。该设计用Verilog语言进行了RTL级描述,然后用Modelsim对电路进行了仿真,经Quartus综合以后在FPGA上进行了验证。实验表明,在Altera的芯片EP2C35F672C8上,该设计最高工作时钟可达63.37MHz,可以作为IP核应用于JPEG2000图像编码芯片中。arithmetic coding algorithm is an efficient technique for lossless data compression, which has been adopted in JPEG2000 standard. The algorithm is studied, then the VLSI architecture is proposed to implement the arithmetic coder which can be easily implemented by hardware. The Verilog HDL coding of the arithmetic cosing is designed and simulated with Modelsim, the coder is then verified with FPGA. Experimental result shows that the encoder can work up to 63.37 MHz on Altera＇s EP2C35F672C8. This architecture can be used as a compact and efficient IP core for JPEG2000 VLSI implementation.

关 键 词：无损数据压缩 JPEG2000 算术编码器 FPGA 

分 类 号：TN47[电子电信—微电子学与固体电子学]