双输出DC-DC的内建可测性设计  

The Design of the Build-in Testability of a Dual Output DC-DC

作　　者：张倩[1] 来新泉[2] 郭仲杰[2] 叶强[2] 

机构地区：[1]西安音乐学院基础部计算机教研室,西安710061 [2]西安电子科技大学CAD所,西安710071

出　　处：《电子器件》2008年第2期550-554,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金资助(60172004);国家教育部博士点基金资助(20010701003);西安应用材料创新基金资助(XA-AM-200504)

摘　　要：双路输出的DC-DC转换器设计中有许多参数需要检测和控制,非常有限的引脚数目使得直接测试内部参数比较困难。本设计大胆采用管脚复用技术,在增加很小内部电路的基础上,设计了一款新颖、实用的双路输出DC-DC的内部测试电路,并经Cadence、Hspice等EDA软件对设计电路进行仿真,各项指标均符合设计要求,从而完成芯片的可测性设计,并大大缩短了芯片的研制周期,提高了产品利润。There are many parameters to be detected and controlled during the design of a dual, synchronous, high efficiency and current mode DC-DC converter, but it is difficulty for the designer to detect them directly with the limited PAD. This paper shows that a novel, practical test circuit buils on the chip, based on a few increasing of the circuit, with the technology of multi-function of the PAD. According to the calculation and simulation using Cadence, Hspice and etc, the results are satisfied all the requirements that we have designed. Therefore, it can complete the Testability of the chip, and greatly shorten the period of the chip designing, improve the gain of the production.

关 键 词：双输出DC-DC 内建测试 可测性设计 管脚复用 

分 类 号：TN432[电子电信—微电子学与固体电子学]