基于AD9850的倍频器设计  

Design of frequency multiplier based on AD9850

作　　者：阮伟华[1] 

机构地区：[1]南京工业职业技术学院电气自动化系,江苏南京210016

出　　处：《国外电子元器件》2007年第12期23-26,共4页International Electronic Elements

摘　　要：介绍基于直接数字频率合成器(DDS)AD9850的倍频器设计,倍频倍数N可以在限定范围内自行设置。系统主要模块CPLD/FPGA、DDS(AD9850)和单片机(80C51)之间可以并行通信,具有编程控制简便、接口简单、成本低、易于实现系统小型化等优点。在定时、算法精确的前提下,倍频后的波形平均精度达到10-3。The design of frequency multiplier based on AD9850 which is a kind of DDS＇s chip is introduced in this paper,and the frequency multiplier coefficient N can be set in one limited scope. The three major modules-CPLD/FPGA, AD9850 and 80C51 work in the parallel ways.The system has a lot of advantages--it＇s easy to be controlled, and it＇s easy to be connected, and it has low cost, and it＇s easy to realize the small system,and so on.The average accuracy of the output wave can reach 10^-3 when the timer and the arithmetic are accurate.

关 键 词：直接数字频率合成器(DDS) CPLD/FPGA 倍频器 AD9850 

分 类 号：TN742.1[电子电信—电路与系统]