BM迭代算法的循环架构设计及实现  

Cycle architecture design of BM iterative algorithm and its implementation

作　　者：陈黎明[1] 邓林江[1] 王琳[1] 

机构地区：[1]重庆邮电大学编码技术研究所,重庆400065

出　　处：《重庆邮电大学学报（自然科学版）》2008年第2期175-178,共4页Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)

基　　金：国家自然科学基金项目(60272005);教育部新世纪优秀人才支持计划(NCE-04-0601)

摘　　要：BCH码的译码问题主要归结为一个关键方程的解决,即错误位置多项式的求解,BM迭代算法自1966年由Berlekamp-Massey提出以来经过不断改进,已经成为解决这一问题的成熟算法。提出了一种适合硬件实现的BM迭代算法的循环架构设计,并在此架构下分别实现了基于BM迭代算法和其简化算法的二元BCH(15,5)的FPGA译码器,显示出这一循环架构易于模块移植的优点。仿真结果表明:码组中任意不大于3 bit的随机错误都可以给予纠正。Solving the key equation is the key for the decoding of BCH codes, namely finding error location polynomials, Berlekamp-Massey （BM） iterative algorithm has been improved continuously since it has been proposed in 1966, and it is a mature algorithm for solving this problem. A cycle architecture of BM iterative algorithm is improved for hardware implementation, and the decoder FPGA implementation based on BM iterative algorithm and its simplified one for a binary BCH （ 15,5 ） are investigated under the architecture. The excellent quality of module-reused by the architecture is shown, Simulation results indicate that three or less than three error bits can be corrected by the hardware implementation.

关 键 词：BM迭代算法 现场可编程逻辑阵列 循环架构设计 

分 类 号：TN911.22[电子电信—通信与信息系统]