埋栅型静电感应器件研制中的外延技术  

Epitaxial Technology for Buried-Gate Static Induction Device

作　　者：雷景丽[1] 李思渊[2] 李海蓉[2] 李海霞[3] 

机构地区：[1]兰州理工大学理学院,兰州730050 [2]兰州大学物理科学与技术学院,兰州730000 [3]中国科学院中国近代物理研究所,兰州730000

出　　处：《半导体技术》2008年第5期384-387,共4页Semiconductor Technology

基　　金：甘肃省攻关项目(GS012-A52-064)

摘　　要：对电力埋栅型静电感应晶体管关键工艺外延进行了深入研究,提出了在低阻p型衬底上制备高阻n型外延层的工艺方法,使外延层的方块电阻达到40000Ω/□。实验证明,该方法能有效抑制自掺杂效应和扩散效应,避免了外延过程中可能出现的反型。研制的电力埋栅型静电感应晶体管I-V特性良好、栅源击穿电压达到70V,阻断电压达到600V。Epitaxial process, the key process, to buried-gate static induction device was studied, and methods for making high n-type resistance epilayer on low p-type resistance underlay were provided, the epitaxial square resistance was up to 40 000Ω/□. Experiments prove that these methods can restrain selfdoping and diffusion effect and avoid causing contrary epilayer, the I-V characteristics of static induction transistor manufactured by the methods are reasonable, the breakdown voltage is upgraded to 70 V and the cut voltage is also up to 600 V.

关 键 词：工艺 外延层 反型 自掺杂 

分 类 号：TN304.054[电子电信—物理电子学]