基于场的寄生电容并行提取方法  

Parallel method for field-based IC parasitic capacitance extraction

作　　者：孙世磊[1,3] 薛金涛[2] 王高峰 姬晓辉[4] 

机构地区：[1]武汉大学计算机学院,湖北武汉430072 [2]复旦大学微电子国家重点实验室,上海200433 [3]武汉大学微电子与信息技术研究院,湖北武汉430072 [4]武汉大学经济与管理学院,湖北武汉430072

出　　处：《武汉大学学报（工学版）》2008年第2期103-106,110,共5页Engineering Journal of Wuhan University

基　　金：国家自然科学基金资助项目(编号:90307017)

摘　　要：在集成电路版图寄生参数提取中,基于场的方法虽然能够提供更为精确的结果,却由于时间及空间复杂度等问题无法直接应用于复杂互连线网络参数提取.针对这一问题对复杂导体进行切分,并结合分治法和并行计算技术加速参数提取,解决由于互连线网络过于庞大引起基于场的提取引擎失效的问题,并能够提供较精确的分布式参数.In integrated circuit （IC） layout parasitic extraction, field-based methods can provide more sophisticated result; but it can not be employed directly in complex interconnect parasitic extraction due to time and space complexity issues. In this paper, complex conductor is divided into segments; and the extraction is accelerated by dividing and-conquering and parallel computation method. By virtue of this technique, the slowdown of the field based solver caused by large-scale interconnect networks can be overcome. Moreover, this new approach is able to provide more accurate distributed parameters.

关 键 词：集成电路 电容 寄生参数 并行计算 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]