一种MEMS压控电容设计及其相位噪声分析  

Design of a MEMS varactor and Analysis of its Phase Noise

作　　者：王政[1] 刘泽文[1] 

机构地区：[1]清华大学微电子所,北京100084

出　　处：《功能材料与器件学报》2008年第2期539-543,共5页Journal of Functional Materials and Devices

摘　　要：给出了一种MEMS压控电容的设计和相位噪声分析结果。在电容器结构中引入衬底金属层以达到控制寄生电容的目的;使用HFSS进行了上极板开孔对电容的影响的仿真,得到了不影响电容值的最佳尺寸是5微米。在恒寄生电容的假设下分析了MEMS压控电容的相位噪声,在SPICE模型基础上使用HSPICE进行了相位噪声仿真,分析发现布朗运动所产生的相位噪声的典型值是-176dBc/Hz,环境声波造成的相位噪声的典型值是-137dBc/Hz。Design and phase noise analysis of a MEMS varactor is presented. Metal layer on the substrate is used to control the parasitic capacitance in the configuration. The effect of etch hole on the up - capacitor electrode is simulated using HFSS, and the best size which will not effect the capacitance is found to be 5 μm. On the assumption of the constant parasitic capacitance, the phase noise of MEMS varactor is analysed. Based on a SPICE model, simulations of phase noise have been performed using HSPICE. It＇s found that the typical phase noise due to Brownian motion is -176dBc/Hz, and acoustic noise is - 137 dBc/Hz.

关 键 词：MEMS压控电容 可控寄生电容 刻蚀孔 相位噪声 

分 类 号：TB308[一般工业技术—材料科学与工程]