RFID ASK100%、10%调制时钟产生电路设计  

Design of a Clock Generator for RFID with ASK 100%,10% Modulation

作　　者：杨俊焱[1] 戴宇杰[1] 张小兴[1] 吕英杰[1] 樊勃[1] 

机构地区：[1]南开大学微电子所,天津300071

出　　处：《微纳电子技术》2008年第5期302-306,共5页Micronanoelectronic Technology

基　　金：天津市科技发展计划项目(05YFGZGX02300)

摘　　要：设计了一种时钟产生电路,该电路采用基于低功耗锁相环(PLL)的方法,用于产生13.56MHz ASK100%、10%调制射频卡所需要的时钟。针对射频识别(RFID)系统,锁相环采取了特殊的设计。本电路作为模块可应用于符合ISO/IEC15693、ISO/IEC18000-3标准的非接触IC卡中。通过Cadence spectre软件,使用0.35μm互补金属氧化物半导体(CMOS)工艺模型进行验证。仿真结果显示:电路采用3.3V电源供电时,100%调制载波幅度为0%时,总工作电流仅为17μA。A clock generator based on the low power phase-locked loop （LLP）, which is capable of generating clock for radio frequency identification （RFID） with ASK 100% and 10% modulation was designed. The PLL was designed specially in order to be used in RFID systems. It can be used in the contactless smart card in accordance with ISO/IEC 15693. ISO/IEC 18000-3 standards. The circuit design was realized in 0.35 μm CMOS technology. The simulation shows that the total current consumption is only 17 μA at 3, 3 V with ASK 100% modulation of 0% amplitude.

关 键 词：射频识别 锁相环 幅度调制 时钟产生 互补金属氧化物半导体 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN432