Optimization and Application of SRAM in 90nm CMOS Technology  

90nm CMOS工艺SRAM的优化及应用(英文)

作　　者：周清军[1] 刘红侠[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件国家重点实验室,西安710071

出　　处：《Journal of Semiconductors》2008年第5期883-888,共6页半导体学报（英文版）

基　　金：国家自然科学基金(批准号:60206006);国防预研基金(批准号:51308040103);西安应用材料创新基金(批准号:XA-AM-200701)资助项目~~

摘　　要：This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.提出了一种优化的SRAM,它的功耗较低而且能够自我修复.为了提高每个晶圆上的SRAM成品率,给SRAM增加冗余逻辑和E-FUSE box从而构成SR SRAM.为了降低功耗,将电源开启/关闭状态及隔离逻辑引入SR SRAM从而构成LPSR SRAM.将优化的LPSR SRAM64K×32应用到SoC中,并对LPSR SRAM64K×32的测试方法进行了讨论.该SoC经90nm CMOS工艺成功流片,芯片面积为5.6mm×5.6 mm,功耗为1997mW.测试结果表明:LPSR SRAM64K×32功耗降低了17.301 %,每个晶圆上的LPSRSRAM64K×32成品率提高了13.255 %.

关 键 词：OPTIMIZATION LPSR SRAM redundancy logic power on/off states 

分 类 号：TN432[电子电信—微电子学与固体电子学]