一种用于流水线ADC的高速采样保持电路  

A High-Speed Sample and Hold Circuit for Pipelined A/D Converter

作　　者：姜申飞[1] 戴庆元[1] 王冬辉[1] 赵懿[1] 

机构地区：[1]上海交通大学微纳科学技术研究院,上海200030

出　　处：《微处理机》2008年第1期19-21,共3页Microprocessors

摘　　要：介绍了一种适用于10位80MS/s流水线模数转换器(Pipelined ADC)的采样/保持(S/H)电路。该电路为开关电容结构,以0.25μm CMOS工艺实现。采用栅源电压恒定的栅压自举开关和底极板采样技术,极大地减小了采样的非线性失真。基于该S/H电路的流水线A/D转换器在80MHz采样率下,输入信号为奈奎斯特频率时,无杂散动态范围(SFDR)为84.9dB,有效位数(ENOB)达到10位。In this paper, a sample and hold circuit for a 10bit 80MS/s pipelined A/D converter has been designed, which is implemented in a TSMC 0.25μm CMOS process. The S/H circuit is realized in switched- capacitor topology. Using switch gate voltage bootstrapping for constant Vgs and bottom plate sampling techniques, nonlinear distortion is reduced significantly. The A/D converter based on this S/H circuit achieves a SFDR of 84.9dB at 80MHz sampling rate.

关 键 词：采样保持电路 流水线模数转换器 栅压自举开关 共模反馈 开关电容 

分 类 号：TN432[电子电信—微电子学与固体电子学]