基于FPGA的增量式光电编码器计数电路设计  

Design of the circuit of counting for incremental encoder based on FPGA

作　　者：何勇[1] 范永坤[1] 王涛[1] 王仁杰[1] 

机构地区：[1]中国科学院光电技术研究所

出　　处：《仪器仪表用户》2008年第3期90-92,共3页Instrumentation

摘　　要：本文介绍了一种基于现场可编程门阵列(FPGA)的光电编码器数据采集系统,提出了测速算法-变M/T法,讲述了鉴相、四倍细分及测速的原理。并给出了硬件设计电路。A kind of data collection system of incremental encoders is introduced based on FPGA, proposed a way of measure velocity-the method of alterable M/T, and described the principle of the four foldfrequency subdivision, the direction-judgment and the method of measure velocity. And the hardware circuit design was also given.

关 键 词：光电编码器 鉴相 四倍细分 测速 

分 类 号：TN6[电子电信—电路与系统]