运算精简的蒙哥马利算法模乘器设计  

Operation Reduced Montgomery’s Algorithm Modular Multiplier Design

作　　者：蒋晓娜[1] 段成华[1] 

机构地区：[1]中国科学院研究生院信息科学与工程学院,北京100049

出　　处：《计算机仿真》2008年第5期101-104,共4页Computer Simulation

基　　金：国家"863计划"项目资助(2002AA141041)

摘　　要：针对Montgomery算法的可伸缩脉动阵列模乘协处理器的硬件实现中,速度和面积没有取得很好平衡的问题,结合Walter等学者对Montgomery算法的分析,利用EDA仿真分析工具,提出一种运算精简的蒙哥马利算法模乘器设计方法。该方法通过先分析已有Montgomery算法,得到运算精简蒙哥马利算法,然后将该算法映射到可伸缩脉动阵列结构,使模乘器在速度和面积上能够取得很好的平衡。最后进行仿真实验验证,结果证明该方法解决了模乘器速度和面积平衡的问题。通过该方法设计的模乘器,用TSMC0.18μm标准单元库综合,核心运算单元最高时钟频率可达385MHz,等效单元1.2k等效门。与现有其他方法相比,该模乘器在平衡方面取得较好性能,可以拓展其在移动通信领域的应用。In view of the problem that area×time factor of modular multiplication coprocessor, when using Scalable Systolic Array circuit scheme to implement Montgomery algorithm, can not get the trade-offs, and by combining the available typical Montgomery Modular algorithms and using EDA simulation tools, an operation reduced radix 2 - Montgomery algorithm Modular Multiplier design scheme is developed. In this scheme, in order to get the trade - offs of area × time factor, map an operation reduced radix 2 - Montgomery algorithm, which is developed by combining the available typical Montgomery Modular algorithms, to a Scalable Systolic Array. And the simulation result verifies the scheme. The result shows that based on the TSMC 0.18 μm CMOS technology, area of the Modular Multiplier is about 1.2k equivalent-gate, the key cell frequency can up to 385MHz. Compared with other existing solutions, this modular multiplication coprocessor has advantage in terms of area×time factor, and can be used widely in mobile communication field.

关 键 词：蒙哥马利算法 可伸缩脉动阵列 公钥密码体制 

分 类 号：TN47[电子电信—微电子学与固体电子学]