面向SoC系统芯片中跨时钟域设计的模型检验方法  

Model Checking on Clock Domain Crossing Design of System-on-Chip

作　　者：冯毅[1] 易江芳[1] 刘丹[1] 佟冬[1] 程旭[1] 

机构地区：[1]北京大学微处理器研究与开发中心,北京100871

出　　处：《电子学报》2008年第5期886-892,共7页Acta Electronica Sinica

基　　金：国家863高技术研究发展计划(No.2006AA010202)

摘　　要：传统方法无法在RTL验证阶段全面验证SoC系统芯片中的跨时钟域设计.为解决此问题,本文首先提出描述亚稳态现象的等价电路实现,用以在RTL验证中准确体现亚稳态现象的实际影响;然后使用线性时序逻辑对跨时钟域设计进行设计规范的描述;为缓解模型检验的空间爆炸问题,进一步针对跨时钟域设计的特点提出基于输入信号的迁移关系分组策略和基于数学归纳的优化策略.实验结果表明本文提出的方法不仅可以在RTL验证阶段有效地发现跨时钟域设计的功能错误,而且可以使验证时间随实验用例中寄存器数量的递增趋势从近似指数级增长减小到近似多项式级增长.Traditional approach in RTL verification cannot completely verify the clock domain crossing （CDC） design of SoC. To solve this problem, we first propose a RTL module to model the actual effect of metastability. Then, linear temporal logic is proposed to model the specification of CDC designs. To solve the exponential problem in model checking, based on the characteristic of CDC designs, a strategy on input signal partition for the state transition＇ s characteristic function and a strategy on induction are proposed. Experiment results demonstrate that our method is useful to find CDC errors in the RTL verification stage and the verification time is approximately reduced from exponential to polynomial increased with the register size.

关 键 词：形式化验证 模型检验 跨时钟域设计 线性时序逻辑 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]