基于可测性分析的高层次寄存器分配算法  

High level register allocation algorithm based on testability analysis

作　　者：成本茂[1] 王红[1] 杨士元[1] 牛道恒[1] 靳洋[1] 

机构地区：[1]清华大学自动化系,北京100084

出　　处：《东南大学学报（自然科学版）》2008年第3期396-400,共5页Journal of Southeast University：Natural Science Edition

基　　金：国家重点基础研究发展计划(973计划)资助项目(2005CB321604);国家自然科学基金资助项目(60633060).

摘　　要：为了提高综合后电路的可测性,提出了一种面向电路可测性的寄存器分配方案.该方案首先从已调度的数据流图着手,建立了一种可用于高层次综合的行为级可测性分析方法:对算子模块的门级实现进行门级可测性分析,并进而抽象出算子的行为级可控性/可观性值;在数据流图中,逐级计算出各节点变量的行为级可测性指标;然后按照最大改善可测性指标的原则,进行寄存器分配.在标准电路上的实验表明,除了较小的面积开销外,电路的可测性优于所对照的其他2种方法.A testability-oriented register allocation scheme is presented in this paper. The scheme begins from the scheduled data flow graph （SDFG）, and an effective behavioral level testability meas- urement is given： after testability analysis done to the gate-level implementation of common operators, the behavioral controllability/observability of the operators is abstracted; Then behavioral testability of each node in SDFG is calculated step by step. Registers are allocated according to the rule of getting maximal improvement of testability. Experimental results on some benchmark circuits show that the proposed scheme can get higher fault coverage and better timing performance compared with other register allocation schemes at little area overhead.

关 键 词：高层次综合 寄存器分配 可测性 已调度数据流图 

分 类 号：TN74[电子电信—电路与系统]