基于FPGA的数字秒表的设计  

Design of Digital Stopwatch Based on FPGA

作　　者：杨远成[1] 赵创社[1] 雷金利[1] 

机构地区：[1]西安应用光学研究所,陕西西安710065

出　　处：《现代电子技术》2008年第12期52-54,共3页Modern Electronics Technique

摘　　要：以FPGA为核心的数字秒表,具有外围电路少、集成度高、可靠性强等特点。该数字秒表的设计是以VHDL为开发工具,以QuartusⅡ为软件平台,采用模块化设计,并通过数码管驱动电路动态显示计时结果。给出部分模块的VHDL源程序和仿真结果,仿真结果表明该设计方案的正确,展示了VHDL语言的强大功能和优秀特性。The digital stopwatch whose core is FPGA with virtue of few periphery electric circuit,high intergration and high reliability. It is modular designed with VHDL language and QUARTUS Ⅱ software. The digital stopwatch can be displayed with the digital driving circuit. The VHDL source program and simulating results of digital stopwatch are given. The simulating results show that the design method is correct, it shows she powerful function and excellent character of the VHDL.

关 键 词：FPGA VHDL 数字秒表 Quartus Ⅱ 

分 类 号：TN702[电子电信—电路与系统]