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出 处:《计算机工程与应用》2008年第19期93-95,共3页Computer Engineering and Applications
摘 要:根据AVS标准中的反扫描、反量化和反变换算法特点提出了一种用于AVS解码芯片中的反扫描、反量化和反变换硬件模块的设计方案,该设计以宏块为单位进行操作,便于集成到整个解码芯片的流水线中。同时,在宏块内实现了8×8子块的流水线操作并进行了优化,在反变换中用RAM代替寄存器堆进行转置操作。综合结果表明,该设计在获得了较高处理速度的同时节省了大量的寄存器和选择器资源。An optimized implementation of inverse scan,inverse quantization and inverse transform for AVS decoder is proposed according to the algorithms in the AVS specification.The implementation is designed on maeroblock level and can be easily mapped as a stage for MB pipelining.Block-pipelining is used during the processing of a macroblock.RAM is used to perform the transPose operation in the inverse transform instead of register stack.The synthesis result indicates that a large sum of registers and Multiplexers are saved and high processing speed is obtained.
分 类 号:TN919.81[电子电信—通信与信息系统]
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