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机构地区:[1]东南大学电子工程系
出 处:《东南大学学报(自然科学版)》1997年第6期118-122,共5页Journal of Southeast University:Natural Science Edition
摘 要:采用真空高频感应加热法制备SrTiO3晶界层电容器半导瓷,研究了掺杂材料、掺杂量、烧结温度、保温时间、成型密度等对半导瓷性能结构的影响.所制备的半导瓷经二次烧结成的SrTiO3BLC,其视在介电常数Keff>3×104,损耗角正切tanδ≈10-2,绝缘电阻率ρ>1010Ω·cm.Semiconductive ceramics of SrTiO_3 based grain boundary barrier layer capacitor were prepared by high frequency induction heating device. The effects of doping materials and amounts, sintering temperature, soaking time, and compaction density on properties and construction of SrTiO_3 based semiconductive ceramics were investigated in this condition. After second firing, SrTiO_3 based BLC with k eff >3×10 4, tan δ ≈10 -2 , ρ >10 10 Ω·cm was achieved.
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