基于FPGA的高速RS编解码器设计与实现  

Design and implementation of fast RS encoder and decoder based on FPGA

作　　者：顾艳丽[1] 周洪敏[1] 

机构地区：[1]南京邮电大学光电工程学院,南京210003

出　　处：《信息技术》2008年第6期48-50,共3页Information Technology

摘　　要：详细介绍了RS(255,191)编解码器的设计,按照自上而下的设计流程给出了算法的FPGA实现。根据编解码器的不同特点,采用不同方法实现GF(28)乘法器。编码器采用并行结构、解码器采用并行无逆的BM算法实现关键模块,求逆器采用查表方法。采用以上方法的组合,使得在资源占用允许的同时最大限度地提高了编解码速度。In this paper, the design of RS （255,191） encoder and decoder is mainly introduced. According to top-down design flow FPGA implementation of this algorithm is given. The multiplier in GF （28 ） was realized by different ways according to their different characteristics. The encoder is designed using parallel structure, the decoder is designed using parallel-inversionless BM algorithm to implement its key module, a look-up table method is adopted to implement inversion. Using a combination of the above methods the paper enhanced the encoding and decoding speeds as maximum as possible under the permission of resources occupancy.

关 键 词：数字视频广播(DVB) RS编解码 现场可编程逻辑阵列(FPGA) BM算法 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]