基于RLC模型的集成电路互连线串扰估计  

Estimation for interconnect crosstalk of integrated circuit based on RLC model

作　　者：李朝辉[1] 

机构地区：[1]燕山大学电子与通信工程系,秦皇岛066004

出　　处：《电子测量技术》2008年第5期49-51,共3页Electronic Measurement Technology

摘　　要：本文提出了一个新的基于RLC模型的高速集成电路互连线串扰峰值估计公式,在考虑了电感效应的基础上建立了RLC电路模型,对CMOS电路器件作了线性假设,推导出了当侵略线输入单位斜升信号时的互连串扰时域表达式。计算机仿真结果表明,该公式的结果相对于HSPICE仿真的误差绝对值小于10%,可被应用于集成电路版图综合的布局规划模型中,能够在高速、高密度VLSI的设计阶段预测信号性能。A new formula for estimating crosstalk peak in VLSI interconnects is presented in the paper, which is based on the RLC model. Considering the coupling inductance effect, a RLC circuit model is built, and a time-domain expression for interconnect crosstalk is derived when there is a normalized saturated ramp signal on the aggressor line. Calculation and experiment show that it can provide accuracy within 10% of HSPICE simulation. The new formula can be easily integrated into crosstalk-aware layout optimization programs for predicting the signal integrity in designing high speed and high density VLSI circuits.

关 键 词：集成电路 互连 串扰 RLC模型 

分 类 号：TN47[电子电信—微电子学与固体电子学]