低功耗、高性能多米诺电路电荷自补偿技术  

Charge Self-Compensation Technology Research for Low Power and High Performance Domino Circuits

作　　者：汪金辉[1] 宫娜[2] 侯立刚[1] 吴武臣[1] 董利民[1] 

机构地区：[1]北京工业大学集成电路与系统研究室,北京100022 [2]河北大学电子信息工程学院,保定071002

出　　处：《Journal of Semiconductors》2008年第7期1412-1416,共5页半导体学报（英文版）

摘　　要：提出了一种电荷自补偿技术来降低多米诺电路的功耗,并提高了电路的性能.采用电荷自补偿技术设计了具有不同下拉网络(PDN)和上拉网络(PUN)的多米诺电路,并分别基于65,45和32nmBSIM4SPICE模型进行了HSPICE仿真.仿真结果表明,电荷自补偿技术在降低电路功耗的同时,提高了电路的性能.与常规多米诺电路技术相比,采用电路自补偿技术的电路的功耗延迟积(PDP)的改进率可达42.37%.此外,以45nmZipperCMOS全加器为例重点介绍了功耗分布法,从而优化了自补偿路径,达到了功耗最小化的目的.最后,系统分析了补偿通路中晶体管宽长比,电路输入矢量等多方面因素对补偿通路的影响.A charge self-compensation technology is proposed in this paper to lower the active power and improve the performance of domino circuits. Domino circuits with different structures of pull-up network （PUN） and pull-down network （PND） are designed using charge self-compensation technology and are simulated based on 65,45, and 32nm BSIM4 SPICE models by the HSPICE tools. The simulation results show that this technology is effective for high performance and low power operation. The power-delay product （PDP） is reduced by up to 42.37% compared to standard domino circuits. Moreover,a novel method for power distribution is introduced. With this method,taking a Zipper CMOS full-adder in 45nm technology as an example,the paths for charge self-compensation is optimized to minimize the power. Finally,the influence of W/L of nMOS and pMOS in the path for charge self-compensation and input of the circuits on this technology is analyzed thoroughly.

关 键 词：自补偿电荷通路 功耗延迟积 ZIPPER CMOS全加器 多米诺电路 

分 类 号：TN79[电子电信—电路与系统]