低功耗异或门的设计  

Low power XOR gate design

作　　者：张爱华[1] 夏银水[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《浙江大学学报（理学版）》2008年第4期409-411,415,共4页Journal of Zhejiang University（Science Edition）

基　　金：国家自然科学基金资助项目(60676017);浙江省自然科学基金人才专项项目(R105614);宁波市自然科学基金资助项目(2006A610091)

摘　　要：在分析了现有典型的异或门电路的基础上,提出了基于传输管逻辑的低功耗异或门的设计.电路实现了内部节点信号的全摆幅,使之具有较强的驱动能力,且避免了后级反相器中亚阈功耗的产生,实现了电路的低功耗.在5、3.3、1.8 V电源下,经PSPICE在0.24μm工艺下模拟,与已发表的异或门电路设计相比,新提出的电路功耗和功耗延迟积的改进分别高达36.5%和68.0%,说明本文设计的异或门电路在功耗和延迟方面具有优势.Based on the analysis of existing XOR gate circuits, a pass transistor based low power XOR gate was proposed. Since the proposed design implements full swing for internal node signals, it improves driven strength and avoids sub-threshold power from succeeded inverters, achieving its low power consumption. Under power supply voltages 5, 3.3, 1.8 V,, using 0.24 μm process to carry out PSPICE simulation, the proposed XOR gate can save power consumption up to 36.5 %, while power-delay-product up to 68.0 % as compared with the published designs, which shows that the proposed design has advantages in power and delay.

关 键 词：低功耗 异或门 传输管 全摆幅 

分 类 号：TN402[电子电信—微电子学与固体电子学]