同步部分并行结构的准循环LDPC码译码器  

A Synchro Partially Parallel Architecture for Quasi-Cyclic LDPC Codes

作　　者：许恩杨[1] 姜明[1] 赵春明[1] 

机构地区：[1]东南大学移动通信国家重点实验室,南京210096

出　　处：《电子与信息学报》2008年第7期1630-1634,共5页Journal of Electronics & Information Technology

基　　金：国家自然科学基金重大项目(60496311);国家863计划项目(2006AA01Z263)资助课题

摘　　要：该文根据准循环LDPC码的结构特点,提出了一种同步部分并行结构的译码器。在译码器中,校验节点处理单元和变量节点处理单元同时并行工作,使得迭代过程中新产生的软信息能够被提前使用,加快迭代的收敛速度。同时,采用差分演化的方法对各节点处理单元的起始位置进行优化,进一步提高了译码器的性能。仿真结果表明,该方案在译码性能和复杂度上都要优于现有其他方案,适合高速译码器的实现。Based on the structure of quasi-cyclic LDPC codes,a synchro partially parallel decoder is proposed in this paper. In the decoder, the check node process units and variable node process units work concurrently, where the new generated soft information is used in advance during the iteration process to accelerate the convergence speed. Furthermore, differential evolution is utilized to optimize the start positions of node process units in order to achieve better performance. Simulation results show that the proposed scheme outperforms others both in performance and complexity, and is very suitable for the implementation of high speed decoders.

关 键 词：低密度奇偶校验(LDPC)码 译码器 同步部分并行结构 

分 类 号：TN911.22[电子电信—通信与信息系统]