资源约束的FPGA流水线调度  

FPGA Pipeline Scheduling Under Resource Constraints

作　　者：宋健[1] 葛颖增[2] 窦勇[1] 

机构地区：[1]国防科技大学计算机学院,长沙410073 [2]河南公安高等专科学校信息安全系,郑州450002

出　　处：《计算机工程》2008年第15期44-46,50,共4页Computer Engineering

基　　金：国家自然科学基金资助项目(60633050)

摘　　要：循环是程序中十分耗时的部分,流水线能够加速循环执行但需要大量运算资源。由于FPGA资源有限,将循环代码在FPGA上加速时手动设计流水线不具有实际可行性。该文使用软件流水将循环自动映射到FPGA上,并实现资源约束下的流水线调度。通过探索整个或者局部资源组合空间,可以选择一个性能和面积比较平衡的设计。Loop is the time-consuming part in program. The pipeline can accelerate its execution but needs too much computing resources. Due to limited resources, it＇s impractical to pipeline the loop by hand in FPGA. In this paper, the loops are mapped automatically onto FPGA using software pipelining, and the pipeline scheduling under resource constraints is implemented. By exploring the whole or part combination space, a design which balances performance and area can be chosen.

关 键 词：流水线 模调度 资源约束 空间探索 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]