深亚微米SoC芯片的可测试性设计  

Design for testability of deep sub-micro SoC chip

作　　者：胡剑[1] 沈绪榜[1] 王涛[1] 

机构地区：[1]西北工业大学计算机学院,西安710072

出　　处：《计算机工程与应用》2008年第23期88-92,共5页Computer Engineering and Applications

摘　　要：深亚微米工艺使SoC芯片集成越来越复杂的功能,测试开发的难度也不断提高。由各种电路结构以及设计风格组成的异构系统使测试复杂度大大提高,增加了测试时间以及测试成本。描述了一款通讯基带SoC芯片的DFT实现,这款混合信号基带芯片包含模拟和数字子系统,IP核以及片上嵌入式存储器,为了满足测试需求,通过片上测试控制单元,控制SoC各种测试模式,支持传统的扫描测试以及专门针对深亚微米工艺的,操作在不同时钟频率和时钟域的基于扫描的延迟测试模式,可配置的片上存储器的BIST操作以及其它一些特定测试模式。With the improvement of complexity and integration ability of SoC chips,more and more challenges can be encountered in the process of test development.Inhomogeneous system formed by different circuit structures and design styles makes test more difficult,which results in long test time and high test cost.This paper mainly presents the DFT implementation of communication baseband SoC chip.This mix-signal SoC chip comprise analog and digital sub-system,IP cores and embedded on- chip memories.All kinds of test mode could he controlled by on-chip test control unit to accomplish test requirement,supporting traditional scan test for stuck-at fault and scan-based delay test which operated in different clock frequencies and clock domains for delay faults which are more and more common in current deep sub-micro teehnology,eonfigurable MBIST test mode and other specific DFT techniques.

关 键 词：系统芯片 可测性设计 测试 测试访问 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]