纯数字时钟50%占空比调节电路设计  

Design of Full-Digital 50% Duty-Cycle Clock Corrector

作　　者：何小威[1] 陈亮[1] 李少青[1] 曾献君[1] 

机构地区：[1]国防科技大学计算机学院,长沙410073

出　　处：《电子器件》2008年第4期1197-1200,共4页Chinese Journal of Electron Devices

摘　　要：利用数控延迟线原理和脉冲电路特性设计实现了一种纯数字方式的高性能时钟50%占空比调节电路FD-DCC（full-Digital Duty-Cycle Corrector），不包括任何反馈环路，可产生无偏时钟。经0．13μm工艺版图实现后的SPICE模拟表明，该电路在200-400MHz频率范围内工作稳定，对占空比在10％～90％范围内的畸变时钟能进行高精度的调节，输出时钟占空比为50％±2％，且输出时钟和原始时钟间相位偏差较小。A simple full-digital 50% duty-cycle corrector （FD-DCC） with the principle of digital delay lines and pulse generators, is presented in this paper with high performance to produce non-skew and high-quality clocks. It does not contain any feedback loop. When designed with a 0. 13 μm CMOS technology, the post SPICE simulation has indicated that it works reliably with the acceptable frequency that ranges from 200 MHz to 400 MHz, the clock duty-cycle which is from 10% to 90% can be corrected with high accuracy, and the output duty-cycle is 50%± 2%. What is more, there are smaller phase shifts between the output and original clocks.

关 键 词：占空比调节电路 无偏时钟 数控延迟线SPICE模拟 

分 类 号：TN786.2[电子电信—电路与系统]